Blue Pearl Software, Inc., headquartered in Santa Clara (California), is a privately held EDA (Electronic Design Automation) company that develops software to improve the productivity of ASIC, FPGA and IP designers. Blue Pearl provides products that automate the generation of timing constraints, validate existing timing constraints and check functional design issues at the functional or register transfer level (RTL) of the digital chip design flow.
Blue Pearl’s software is used by ASIC, FPGA and IP designers early in the design flow, on high-level functional design descriptions of an integrated circuit (IC), to develop higher quality RTL code and to automatically generate comprehensive and accurate timing constraints that significantly improve quality of results (QoR).
Blue Pearl’s customers can significantly reduce time to market, lower design costs, and make the design development schedule more predictable. Incorporating Blue Pearl’s products in the design flow is easy as all inputs and outputs are industry standards. Customers benefit by substantially reducing costs that are incurred by electronic products entering the market with timing or functional design errors.
Blue Pearl Software has developed tools that automate manual tasks at the RTL or high-level, at the front-end of the Timing Path Analysis Flow. By validating timing constraints, generating complete timing constraints for false and multicycle paths and reporting on functional design issues, problems can be fixed early before synthesis and physical implementation processes, reducing the number of iterations in the flow considerably. Iterations can take between 1-4 weeks depending on how late in the flow an issue is found. Customers benefit from a very large return on investment when using Blue Pearl Software’s products.
… offers the capability to visualize clocks and asynchronous clock domain crossings in RTL designs to help users analyze their design for CDC metastability.
Analyze RTL™ Suite
… provides functional design analysis to verify properties, methodology standards and design rules. Reduces time spent writing accurate RTL code that is compatible with tools in digital design flows. Lowers design risk and improves quality of results (QoR).
Clock Domain Crossing
As chip complexity rises, designers are increasingly relying on advanced multi-clocking techniques and IP integration to address their time-to-market, high-performance and low-power requirements. Analyze Plus offers full-chip clock domain crossing (CDC), pre-synthesis longest path and Grey Cell methodologies to solve these critical issues.
… identifies false and multi-cycle paths from RTL descriptions and writes SDC timing constraints for implementation as well as SVA or PSL assertions for verification. Create reduces iterations in the flow to achieve timing closure faster, minimizing design risk.
… delivers real-time visibility to ASIC, FPGA and IP RTL design rule and CDC checks to better assess schedules, risk and overall design quality.